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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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2-Input OR Gate
The MC74HC1G32 is a high speed CMOS 2-input OR gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent LSTTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The MC74HC1G32 output drive current is 1/2 compared to MC74HC series. * * * * * * * High Speed: tPD = 7ns (Typ) at VCC = 5V Low Power Dissipation: ICC = 1A (Max) at TA = 25C High Noise Immunity Balanced Propagation Delays (tpLH = tpHL) Output Drive Capability: 5 LSTTL Symmetrical Output Impedance (IOH = IOL = 2mA) ESD Performance: HBM > 2000V; MM > 200V
MC74HC1G32
DF SUFFIX 5-LEAD SOT-353 PACKAGE SC-88A CASE 419A-01
DT SUFFIX 5-LEAD TSSOP PACKAGE TSOP5 CASE TBD
FUNCTION TABLE
Inputs B1 A2 GND 3 4 Y 5 VCC A L L H H B L H L H Output Y L H H H
Figure 1. Pinout (Top View)
A B
1
H4d
Y Pin 1 d = Date Code
Figure 2. Logic Symbol
Marking Diagram
DEVICE ORDERING INFORMATION
Device Nomenclature Motorola Circuit Indicator MC MC Temp Range Identifier 74 74 Device Function 32 32 Package Suffix DF DT Tape and Reel Suffix T1 T1 Pk Package Type SC-88A TSOP5 T d Reel Tape and R l Size 7-Inch/3000 Unit 7-Inch/3000 Unit
D i Od N b Device Order Number MC74HC1G32DFT1 MC74HC1G32DTT1
Technology HC1G HC1G
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
06/99
(c) Motorola, Inc. 1999
1
REV 0.1
MC74HC1G32
MAXIMUM RATINGS*
Characteristics DC Supply Voltage DC Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Power dissipation in still air Lead temperature, 1 mm from case for 10 s SC-88A TSOP5 (VOUT < GND; VOUT > VCC) Symbol VCC VIN VOUT IIK IOK IOUT ICC PD TL Value -0.5 to +7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 20 12.5 25 200 450 260 Unit V V V mA mA mA mA mW C
Storage temperature Tstg -65 to +150 C * Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- SC-88A Package: -3 mW/_C from 65_ to 125_C -- TSOP5 Package: -6 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Characteristics DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature Range Input Rise and Fall Time VCC = 2.0V VCC = 3.0V VCC = 4.5V VCC = 6.0V Symbol VCC VIN VOUT TA tr , tf Min 2.0 0.0 0.0 -55 0 0 0 0 Max 6.0 VCC VCC +125 1000 600 500 400 Unit V V V C ns
MOTOROLA
2
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
MC74HC1G32
DC ELECTRICAL CHARACTERISTICS
VCC Symbol VIH Parameter Minimum High-Level Input Voltage Test Conditions (V) 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 VIN = VIH or VIL IOH = -20A 2.0 3.0 4.5 6.0 4.5 6.0 2.0 3.0 4.5 6.0 4.5 6.0 0 to 6.0 6.0 1.9 2.9 4.4 5.9 4.18 5.68 2.0 3.0 4.5 6.0 4.31 5.80 0.0 0.0 0.0 0.0 0.17 0.18 0.1 0.1 0.1 0.1 0.26 0.26 0.1 1.0 Min 1.5 2.1 3.15 4.20 0.5 0.9 1.35 1.80 1.9 2.9 4.4 5.9 4.13 5.63 0.1 0.1 0.1 0.1 0.33 0.33 1.0 10 TA = 25C Typ Max TA 85C Min 1.5 2.1 3.15 4.20 0.5 0.9 1.35 1.80 1.9 2.9 4.4 5.9 4.08 5.58 0.1 0.1 0.1 0.1 0.40 0.40 1.0 40 A A V Max TA 125C Min 1.5 2.1 3.15 4.20 0.5 0.9 1.35 1.80 Max Unit V
VIL
Maximum Low-Level Input Voltage
V
VOH
Minimum High-Level Output Voltage VIN = VIH or VIL
V
VIN = VIH or VIL IOH = -2mA IOH = -2.6mA VOL Maximum Low-Level Output Voltage VIN = VIH or VIL VIN = VIH or VIL IOL = 20A
V
VIN = VIH or VIL IOL = 2mA IOL = 2.6mA IIN ICC Maximum Input Leakage Current Maximum Quiescent Supply Current VIN = 6.0V or GND VIN = VCC or GND
V
II I I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIII I I I I IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIII I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I II I I I I I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Cload = 50 pF, Input tr = tf = 6.0ns)
S bl Symbol P Parameter T Test C di i Conditions Min TA = 25C Typ 7.0 TA 85C TA 125C Max 15 Min Max 20 Min Max 25 Ui Unit ns tPLH, tPHL Maximum Propogation Delay, Input A or B to Y VCC = 5.0V CL = 15 pF CL = 50 pF VCC = 2.0V VCC = 3.0V VCC = 4.5V VCC = 6.0V VCC = 5.0V 48 24 12 9.0 100 40 20 17 10 125 50 25 21 15 155 90 35 26 20 tTLH, tTHL Output Transition Time CL = 15 pF CL = 50 pF 5.0 50 22 14 12 5 ns VCC = 2.0V VCC = 3.0V VCC = 4.5V VCC = 6.0V 125 35 25 21 10 155 45 31 26 10 200 60 38 32 10 CIN Maximum Input Capacitance pF Typical @ 25C, VCC = 5.0V CPD Power Dissipation C P Di i i Capacitance (N i (Note 1 ) 1.) pF F 10 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. VHC Data - Advanced CMOS Logic DL203 -- Rev 1 3 MOTOROLA
MC74HC1G32
tr INPUT A or B tPLH 90% 50% 10% tTLH 90% 50% 10%
tf VCC GND tPHL DEVICE UNDER TEST
TEST POINT OUTPUT CL*
OUTPUT Y
tTHL
* Includes all probe and jig capacitance
Figure 3. Switching Waveforms
Figure 4. Test Circuit
OUTLINE DIMENSIONS
DF SUFFIX 5-LEAD SOT-353 PACKAGE SC-88A CASE 419A-01 ISSUE B
G V
DIM A B C D G H J K N S V
A
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MM. INCHES MIN MAX 0.071 0.087 0.045 0.053 0.031 0.043 0.004 0.012 0.026 BSC --- 0.004 0.004 0.010 0.004 0.012 0.008 REF 0.079 0.087 0.012 0.016 MILLIMETERS MIN MAX 1.80 2.20 1.15 1.35 0.80 1.10 0.10 0.30 0.65 BSC --- 0.10 0.10 0.25 0.10 0.30 0.20 REF 2.00 2.20 0.30 0.40
5
4
S
1 2 3
-B-
D 5 PL
0.2 (0.008)
M
B
M
N J C 0.5 mm (min)
SOT-353
H
"T1" PIN ONE TOWARDS SPROCKET HOLE
SOT-353 (5 Pin) DEVICE
0.4 mm (min)
1.9 mm
User Direction of Feed
MOTOROLA
4
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
0.65 mm 0.65 mm
K
EE EE EE EE EE
EE EE EE EE EE EE EE EE
MC74HC1G32
PROPOSED DT SUFFIX 5-LEAD TSSOP PACKAGE TSOP5 CASE TBD ISSUE TBD
A L
5 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. DIM A B C D G H J K L M S MILLIMETERS MIN MAX 2.90 3.10 1.30 1.70 0.90 1.10 0.25 0.50 0.85 1.05 0.013 0.100 0.10 0.26 0.20 0.60 1.25 1.55 0_ 10 _ 2.50 3.00 INCHES MIN MAX 0.1142 0.1220 0.0512 0.0669 0.0354 0.0433 0.0098 0.0197 0.0335 0.0413 0.0005 0.0040 0.0040 0.0102 0.0079 0.0236 0.0493 0.0610 0_ 10 _ 0.0985 0.1181
S
1 2 3
B
D G M 0.05 (0.002) H C K J
DO NOT DESIGN WITH THESE DIMENSIONS - PRELIMINARY
TSOP5 (5 Pin) DEVICE
0.037 0.95 0.074 1.9
0.037 0.95 User Direction of Feed
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
5
EEEE EEE EEEE EEE EEE EEE EEEE EEE EEEE EEE
0.039 1.0
0.094 2.4
0.028 0.7 inches mm
MOTOROLA
MC74HC1G32
10 PITCHES CUMULATIVE TOLERANCE ON TAPE 0.2 mm (0.008") E A0 B1 K0 SEE NOTE 2 SEE NOTE 2
K t TOP COVER TAPE D P2
P0
F
W
+
B0 P
+
+
D1 FOR COMPONENTS 2.0 mm x 1.2 mm AND LARGER
FOR MACHINE REFERENCE ONLY INCLUDING DRAFT AND RADII CONCENTRIC AROUND B0
EMBOSSMENT USER DIRECTION OF FEED
CENTER LINES OF CAVITY
*TOP COVER TAPE THICKNESS (t1) 0.10 mm (0.004") MAX. R MIN. TAPE AND COMPONENTS SHALL PASS AROUND RADIUS "R" WITHOUT DAMAGE BENDING RADIUS
EMBOSSED CARRIER
EMBOSSMENT
10
MAXIMUM COMPONENT ROTATION TYPICAL COMPONENT CAVITY CENTER LINE
100 mm (3.937")
1 mm MAX
TAPE 1 mm (0.039") MAX 250 mm (9.843")
TYPICAL COMPONENT CENTER LINE
CAMBER (TOP VIEW) ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm
Figure 5. Carrier Tape Specifications
EMBOSSED CARRIER DIMENSIONS (See Notes 1 and 2)
Tape Size 8 mm B1 Max 4.35 mm (0.171") D 1.5 +0.1/ -0.0 mm (0.059 +0.004/ -0.0") D1 1.0 mm Min (0.039") E 1.75 0.1 mm (0.069 0.004") F 3.5 0.5 mm (1.38 0.002") K 2.4 mm (0.094") P 4.0 0.10 mm (0.157 0.004") P0 4.0 0.1 mm (0.156 0.004") P2 2.0 0.1 mm (0.079 0.002") R 25 mm (0.98") T 0.3 0.05 mm (0.01 +0.0038/ -0.0002") W 8.0 0.3 mm (0.315 0.012")
1. Metric Dimensions Govern-English are in parentheses for reference only. 2. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to 0.50 mm max. The component cannot rotate more than 10 within the determined cavity
MOTOROLA
6
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
MC74HC1G32
t MAX
1.5 mm MIN (0.06") A 20.2 mm MIN (0.795")
13.0 mm 0.2 mm (0.512" 0.008")
50 mm MIN (1.969")
FULL RADIUS
G
Figure 6. Reel Dimensions
REEL DIMENSIONS
Tape Size 8 mm A Max 330 mm (13") G 8.400 mm, +1.5 mm, -0.0 (0.33", +0.059", -0.00) t Max 14.4 mm (0.56")
DIRECTION OF FEED
BARCODE LABEL POCKET HOLE
Figure 7. Reel Winding Direction
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
7
MOTOROLA
MC74HC1G32
CAVITY TAPE
TOP TAPE
TAPE TRAILER (Connected to Reel Hub) NO COMPONENTS 160 mm MIN
COMPONENTS
TAPE LEADER NO COMPONENTS 400 mm MIN
DIRECTION OF FEED
Figure 8. Tape Ends for Finished Goods
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MOTOROLA
8
MC74HC1G32/D VHC Data - Advanced CMOS Logic DL203 -- Rev 1

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